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may 2012 ? 2012 fairchild semiconductor corp oration www.fairchildsemi.com FL103 ? rev. 1.0.1 FL103 ? primary-side-regulation pw m controller for led illumination FL103 primary-side-regulation pwm controller for led illumination features ? low standby power: < 30mw ? high-voltage startup ? few external component counts ? constant-voltage (cv) and constant-current (cc) control without secondary-feedback circuitry ? green-mode: linearly-decreasing pwm frequency ? fixed pwm frequency at 50khz and 33khz with frequency hopping to solve emi problems ? peak-current-mode control in cv mode ? cycle-by-cycle current limiting ? v dd over-voltage protection (ovp) ? v dd under-voltage lockout (uvlo) ? adjustable brownout detector ? gate output maximum voltage clamped at 15v ? thermal shutdown (tsd) protection ? available in the 8-lead soic package ? application voltage range: 80v ac ~ 308v ac applications ? led illumination ? battery chargers for cellu lar phones, cordless phones, pda, digital cameras, power tools description this third-generation primary-side-regulation (psr) and highly integrated pwm contro ller provides features to enhance the performance of led illumination. the proprietary topology, truecurrent?, enables precise cc regulation and simplified circuit for led illumination applications. the result is lower-cost and smaller led lighting compared to a conventional design or a linear transformer. to minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease pwm frequency under light-load conditions. green mode assists the power supply in meeting the powe r conservation requirements. by using the FL103, led illumination can be implemented with few external components and minimized cost. figure 1. 8-lead soic ordering information part number operating temperature range top mark package packing method FL103m -40c to +125c FL103 8-lead, small -outline package (soic-8) tape & reel
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 2 FL103 ? primary-side-regulation pw m controller for led illumination application diagram figure 2. typical application block diagram + - 16v / 7.5v 3 8 v dd hv x + - + - 0.8v + - leb soft driver v dd 2 gate eav eai 1 cs 2.5v 5 vs 6 gnd protection: ovp (over-voltage protection) uvlo (under-voltage lockout) tsd (thermal shutdown protection) sampling & holder s r q + - 28v auto recovery max. duty v reset peak detector t s slope compensation 2.5v tsd pattern generator v reset t dis osc ... figure 3. internal block diagram
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 3 FL103 ? primary-side-regulation pw m controller for led illumination marking information zxytt FL103 tpm figure 4. top mark pin configuration figure 5. pin configuration pin definitions pin # name description 1 cs current sense . this pin connects a current-sense re sistor to detect the mosfet current for peak-current-mode control in cv mode and provides the output-cur rent regulation in cc mode. 2 gate pwm signal output . this pin uses the internal totem-p ole output driver to drive the power mosfet. it is internally clamped below 15v. 3 v dd power supply . ic operating current and mosfet driv ing current are supplied using this pin. this pin is connected to an external v dd capacitor of typically 10f. the threshold voltages for startup and turn-off are 16v and 7. 5v, respectively. the operating current is lower than 5ma. 4 nc no connect . this pin is connected to gnd or no connection. does not connect any voltage source. 5 vs voltage sense . this pin detects the output voltage information and discharge time based on voltage of auxiliary winding. 6 gnd ground 7 nc no connect 8 hv high voltage . this pin connects to dc link capacitor for high-voltage startup. this pin is connected to an external startup resistor of typically 100k ? . f : fairchild logo z: plant code x: 1-digit year code y: 1-digit week code tt: 2-digit die run code t: package type (m=sop) p: y=green package m: manufacture flow code
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 4 FL103 ? primary-side-regulation pw m controller for led illumination absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v hv hv pin input voltage 500 v v vdd dc supply voltage (1) 30 v v vs vs pin input voltage -0.3 7.0 v v cs cs pin input voltage -0.3 7.0 v p d power dissipation (t a <50c) 660 mw ja thermal resistance, (junction-to-air) +150 c/w jc thermal resistance, (junction-to-case) 39 c/w t j junction temperature -40 +150 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or ir, 10 seconds) +260 c esd (2) electrostatic discharge capability human body model (except hv pin), jedec-jesd22_a114 4.50 kv charged device model (except hv pin), jedec-esd22_c101 1.25 note: 1. all voltage values, except differential vo ltages, are given with respect to gnd pin. 2. all pins: hbm =1500v, cdm =750v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v dd continuous operating voltage 25 v t a operation ambient tem perature -40 +125 c
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 5 FL103 ? primary-side-regulation pw m controller for led illumination electrical characteristics unless otherwise specified, v dd =15v and t a =25c. symbol parameter conditions min. typ. max. units v dd section v dd-on turn-on threshold voltage 15 16 17 v v dd-off turn-off threshold vo ltage 7.0 7.5 8.0 v i dd-op operating current 3.2 5.0 ma i dd-green green mode operating supply current 0.95 1.20 ma v dd-ovp v dd over-voltage protection level 27 28 29 v t d-vddovp v dd ovp debounce time 90 200 350 s high voltage (hv) section v hv-min minimum startup voltage on hv pin 50 v i hv supply current drawn from pin hv v dl =100v 1.5 2.0 5.0 ma i hv-lc leakage current after startup hv=500v, v dd =v dd-off +1v 0.5 3.0 a oscillator section f osc normal frequency center frequency > v o * 0.5 47 50 53 khz frequency hopping range 1.5 2.0 2.5 protection frequency (3) center frequency < v o * 0.5 33 frequency hopping range 1.3 v f-jum-53 frequency jumping point 50khz ? 33khz, vs 1.05 1.25 1.55 v v f-jum-35 33khz ? 50khz, vs 1.28 1.50 1.75 v f osc-n-min minimum frequency at no-load 300 450 600 hz f osc-cm-min minimum frequency at ccm 7 12 17 khz f dv frequency variation vs. v dd deviation v dd =10~25v 1 2 % f dt frequency variation vs. temperature deviation t a =-40c to +105c 15 % voltage sense (v s ) section v r reference voltage for error amps 2.475 2.500 2.525 v v n green-mode starting voltage on eav f osc =2khz 2.5 v v g green-mode ending voltage on eav (3) f osc =1khz 0.5 v v bias-comv adaptive bias voltage dominated by v comv r vs =20k ? 1.4 v i tc ic bias current 7.3 10.0 12.7 a i vs-bo brownout detection current (3) 175 a i vs-min minimum vs current (3) 90v ac , heavy load 227 a i vs-max maximum vs current (3) 264v ac , no load 721 a t dis_min minimum discharging time normal operation (3) f osc =50khz 0.65 s protection area f osc =33khz 2.0 2.6 4.0 continued on the following page?
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 6 FL103 ? primary-side-regulation pw m controller for led illumination electrical characteristics (continued) unless otherwise specified, v dd =15v and t a =25c. symbol parameter conditions min. typ. max. units current sense (cs) section t pd propagation delay to gate output 90 200 ns t min-n minimum on time at no-load v comr =1v 800 975 1150 ns v th threshold voltage for current limit 0.75 0.80 0.85 v v tl threshold voltage on v s pin smaller than 0.5v 0.25 v gate section dcy max maximum duty cycle 60 75 85 % v ol output voltage low v dd =20v, gate sinks 10ma 1.5 v v oh output voltage high v dd =8v, gate sources 1ma 5 v t r rising time c l =1nf 200 250 ns t f falling time c l =1nf 60 100 ns v clamp output clamp voltage v dd =25v 15 18 v thermal shutdown (tsd) section tsd thermal shutdown temperature (3) +140 c tsd hys thermal shutdown hysteresis (3) - +15 c note: 3. these parameters, although guaranteed , are not 100% tested in production.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 7 FL103 ? primary-side-regulation pw m controller for led illumination typical performance characteristics figure 6. v dd-on vs. temperature figure 7. v dd-off vs. temperature figure 8. i dd-op vs. temperature figure 9. f osc vs. temperature figure 10. v r vs. temperature figure 11. i dd-green vs. temperature 15.0 15.4 15.8 16.2 16.6 17.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [ ] vdd -on [v] 7.0 7.2 7.4 7.6 7.8 8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [ ] vdd -off [v] 0 1 2 3 4 5 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [ ] idd -op [ma] 44 46 48 50 52 54 56 -40 -25 -10 5 20 35 50 65 80 95 110 125 f osc [khz] temperature [ ] 2.475 2.485 2.495 2.505 2.515 2.525 -40 -25 -10 5 20 35 50 65 80 95 110 125 v r [v] temperature [ ] 0.80 0.88 0.96 1.04 1.12 1.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [ ] idd -green [ma]
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 8 FL103 ? primary-side-regulation pw m controller for led illumination typical performance characteristics (continued) figure 12. f osc-n-min vs. temperature figure 13. f osc-cm-min vs. temperature figure 14. i hv vs. temperature figure 15. t min-n vs. temperature figure 16. i tc vs. temperature figure 17. v clamp vs. temperature 300 330 360 390 420 450 -40 -25 -10 5 20 35 50 65 80 95 110 125 f osc-n-min [hz] temperature [ ] 10 11 12 13 14 15 16 -40 -25 -10 5 20 35 50 65 80 95 110 125 f osc-cm-min [khz] temperature [ ] 0.0 0.7 1.4 2.1 2.8 3.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 i hv [ma] temperature [ ] 800 850 900 950 1000 1050 1100 1150 -40 -25 -10 5 20 35 50 65 80 95 110 125 t min-n [ns] temperature [ ] 8.0 8.8 9.6 10.4 11.2 12.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 i tc [ua] temperature [ ] 14.0 14.8 15.6 16.4 17.2 18.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 v clamp [v] temperature [ ]
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 9 FL103 ? primary-side-regulation pw m controller for led illumination typical performance characteristics (continued) figure 18. v f-jum vs. temperature figure 19. v f-jum-hys vs. temperature 1.05 1.13 1.21 1.29 1.37 1.45 -40 -25 -10 5 20 35 50 65 80 95 110 125 v f-jum [v] temperature [ ] 1.30 1.38 1.46 1.54 1.62 1.70 -40 -25 -10 5 20 35 50 65 80 95 110 125 v f-jum-hys [v] temperature [ ]
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 10 FL103 ? primary-side-regulation pw m controller for led illumination functional description figure 20. basic circuit of a psr flyback converter for led illumination figure 20 shows the basic circuit diagram of a primary- side regulated flyback converter with typical waveforms shown in figure 21. generally, discontinuous conduction mode (dcm) operation is preferred for primary-side regulation since it allows better output regulation. s a f n n v s p pk n n i s a o n n v figure 21. waveforms of dcm flyback converter the operation principles of dcm flyback converter are as follows: stage i during the mosfet on time (t on ), input voltage (v dc ) is applied across the primary-side inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. stage ii when the mosfet (q1) is tu rned off, the energy stored in the inductor forces the rectifier diode (d f ) to be turned on. while the diode is conducting, the output voltage (v o ), together with diode forward-voltage drop (v f ), is applied across the secondary-side inductor and the diode current (i f ) decreases linearly from the peak value (i pk n p /n s ) to zero. at the end of inductor current discharge time (t dis ), all the energy stored in the inductor has been delivered to the output. stage iii when the diode current reaches zero, the transformer auxiliary winding voltage (v a ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the effective capacitor l oaded across mosfet (q1). constant voltage regulation during the inductor current discharge time (t dis ), the sum of output voltage (v o ) and diode forward-voltage drop (v f ) is reflected to the auxiliary winding side as (v o +v f ) n a /n s . since the diode forward-voltage drop (v f ) decreases as current decreases, the auxiliary winding voltage (v a ) reflects the output voltage (v o ) at the end of diode conduction time (t dis ), where the diode current (i f ) diminishes to zero. by sampling the winding
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 11 FL103 ? primary-side-regulation pw m controller for led illumination voltage at the end of the diode conduction time (t dis ), the output voltage (v o ) information can be obtained. the internal error amplifier for output voltage regulation ( eav ) compares the sampled voltage with an internal precise reference to generate error voltage ( v comv ), which determines the duty cycle of the mosfet ( q1 ) in constant voltage mode. constant current regulation the output current ( i o ) can be estimated using the peak drain current ( i pk ) and inductor current discharge time ( t dis ) since output current ( i o ) is same as the average of the diode current ( i f_avg ) in steady state. the output current estimator ( i o estimator ) determines the peak value of the drain current with a peak detection circuit and calculates the output current ( i o ) using the inductor discharge time ( t dis ) and switching period ( t s ). this output information is compared with an internal precise reference to generate error voltage ( v comi ), which determines the duty cycle of the mosfet ( q1 ) in constant current mode. wi th fairchild?s innovative technique truecurrent?, constant current output can be precisely controlled. voltage and current error amplifier of the two error voltages, v comv and v comi , the small one determines the duty cy cle. therefore, during constant voltage regulation mode, v comv determines the duty cycle while v comi is saturated to high. during constant current regulation mode, v comi determines the duty cycle while v comv is saturated to high. operating current the operating current is ty pically 3.2ma. the small operating current results in higher efficiency and reduces the v dd capacitor (c vdd ) requirement. once FL103 enters green mode, the operating current is reduced to 0.95ma, assist ing the power supply in meeting power conservation requirements. green mode operation the FL103 uses voltage regulation error amplifier output (v comv ) as an indicator of the output load and modulates the pwm frequency, as shown in figure 22. the switching frequency decreases as load decreases. in heavy load conditions, the switching frequency is fixed at 50khz. once v comv decreases below 2.5v, the pwm frequency linearly decreases from 50khz. when FL103 enters into green load, the pwm frequency is reduced to a minimum frequency of 370hz., gaining power saving power to help meet international power conservation requirements. figure 22. switching frequency as output load frequency hopping emi reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the emi test equipment. FL103 has an internal frequency hopping circuit that changes the switching frequency between 47khz and 53khz. high-voltage startup figure 23 shows the startup block. the hv pin is connected to the line input or dc link capacitor (c dc ). during startup, the internal startup circuit is enabled. meanwhile, line input supplies the current (i start ) to charge the v dd capacitor (c vdd ). when the v dd voltage reaches v dd-on (16v) and v dc is enough high to avoid brownout, the internal startup circuit is disabled, blocking i start from flowing into the hv pin. once the ic turns on, c vdd is the only energy source to supply the ic consumption current before the pwm starts to switch. thus, c vdd must be large enough to prevent v dd-off (7.5v) before the power can be delivered from the auxiliary winding. to avoid the surge from input source, the r start is connected between c dc and hv, with a recommended value of 100k ? . figure 23. startup block protections the FL103 has several self-protection functions; over- voltage protection, therma l shutdown protection, brownout protection, and pulse-by-pulse current limit. v dd under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 16v and 7.5v, respectively. during startup, the v dd capacitor (c vdd ) must be charged to 16v. the v dd capacitor (c vdd ) continues to supply v dd until power can be delivered from the auxiliary winding of the main transformer. v dd is not allowed to drop below 7.5v during this startup process. this uvlo hysteresis window ensures that v dd capacitor (c vdd ) properly supplies v dd during startup. v dd over-voltage protection (ovp) the ovp prevents damage from over-voltage conditions. if the v dd voltage exceeds 28v at open-loop feedback condition, the ovp is triggered and the pwm switching is disabled. the ovp has a debounce time (typically 200s) to prevent false triggering due to switching noises. thermal shutdown protection (tsd) the built-in temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 140c. there is a hysteresis of 15c.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 12 FL103 ? primary-side-regulation pw m controller for led illumination pulse-by-pulse current limit when the current sensing voltage (v cs ) across the current-sense resistor (r sense ) of mosfet (q1) exceeds the internal threshold of 0.8v, the mosfet (q1) is turned off for the remainder of switching cycle. in normal operation, the pulse-by-p ulse current limit is not triggered because the peak cu rrent is limited by the control loop. leading-edge blanking (leb) each time the power mosfet (q1) switches on, a turn- on spike occurs at the sense resistor (r sense ). to avoid premature termination of th e switching pulse, a leading- edge blanking time is built in. conventional rc filtering can be omitted. during this blanking period, the current- limit comparator is disabled and cannot switch off the gate driver. gate output the FL103 output stage is a fa st totem-pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 15v zener diode to protect power mosfet transistors against undesired over-voltage gate signals. built-in slope compensation the sensed voltage across the current-sense resistor is used for current mode control and pulse-by-pulse current limiting. built-in slope compensation improves stability and prevents sub-harm onic oscillations due to peak-current mode control. the FL103 has a synchronized, positive-slope ramp built-in at each switching cycle. noise immunity noise from the current sens e or the control signal can cause significant pulse-width jitter, particularly in continuous-conduction mode. while slope compensation helps alleviate these problems, further precautions should still be ta ken. good placement and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components near the FL103, and increasing the power mosfet gate resistance are advised. operation area figure 24 shows operation area. FL103 has two switching frequency (f s ) in constant current mode. one is 50khz. in this case, FL103 can be operated with best condition for led illumination. the output voltage range is between normal output voltage (v o n ) and 50% of normal output voltage (v o n ). the other is 33khz. when the output voltage is dropped, by increased load and decreasing the number of le ds, the output voltage (v o ) drops under 50% of normal voltage (v o n ). at that time, v dd drops to near uvlo protection and triggers protection. to avoid 33khz, v o n should be designed with enough margin. figure 24. operation area
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FL103 ? rev. 1.0.1 13 FL103 ? primary-side-regulation pw m controller for led illumination physical dimensions figure 25. 8-lead, small outline package (soic-8) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern st andard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge
? 2012 fairchild semiconductor co rporation www.fairchildsemi.com FL103 ? rev. 1.0.1 14 FL103 ? primary-side-regulation pw m controller for led illumination

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